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Difficulty: Very hardStorage Devices and Interfaces

A technician installs a secondary M.2 NVMe PCIe 4.0 x4 solid-state drive into a workstation motherboard's secondary slot (M2_2). Upon booting into the operating system, disk diagnostic tools report that the drive is operating at only PCIe 4.0 x2 speed. Additionally, two onboard SATA ports (SATA_5 and SATA_6) are no longer recognized by the system. The motherboard technical manual states that the chipset utilizes multiplexed high-speed I/O lanes between storage features. Which of the following best explains why the secondary M.2 drive bandwidth is reduced and the SATA ports are disabled?

  1. The chipset shares bandwidth between the secondary M.2 slot and the SATA controller, disabling specific SATA ports to allocate two PCIe lanes to the M.2 slot.Answer
  2. B
    The newly installed M.2 drive uses an M-key connector that forces the motherboard storage controller to drop to legacy SATA protocol signaling for secondary storage devices.
  3. C
    The storage controller in the system UEFI/BIOS is configured for AHCI mode instead of NVMe mode, capping overall interface throughput across secondary slots.
  4. D
    The secondary M.2 slot routes through an integrated SATA Express bridge chip that converts PCIe signals into dual-channel SATA data streams.

Answer

The motherboard chipset shares high-speed I/O lanes between the secondary M.2 slot and the onboard SATA controller, resulting in lane multiplexing that disables the SATA ports while limiting the M.2 drive to two PCIe lanes.
Motherboard chipsets contain a limited number of Flexible High-Speed I/O (HSIO) lanes. To offer expanded connectivity on mainboards, manufacturers multiplex these lanes between secondary M.2 slots and secondary SATA ports. When an M.2 NVMe drive is inserted into a shared slot, the chipset reallocates lanes, supplying two PCIe lanes to the M.2 slot while turning off the shared SATA ports (SATA 5/6).

Step-by-Step Solution

1
Analyze the reported hardware symptom.
The secondary M.2 NVMe SSD runs at PCIe 4.0 x2 (instead of its rated x4 width), and SATA ports 5 and 6 are simultaneously disabled.
This simultaneous behavior indicates a shared hardware resource bottleneck rather than a drive defect.
2
Evaluate motherboard chipset architecture constraints.
Motherboard chipsets feature a finite number of High-Speed I/O (HSIO / Flexible I/O) lanes divided among PCIe slots, SATA controllers, and USB hubs.
When HSIO lanes are shared, populating a secondary M.2 slot forces the motherboard to reallocate lanes from SATA ports to the M.2 slot, leaving the M.2 slot operating at x2 width and disabling the corresponding SATA ports.
3
Distinguish between chipset lane sharing and protocol/keying misconceptions.
The M-key physical form factor and NVMe protocol support PCIe x4 natively; software settings like AHCI do not disable physical hardware SATA ports.
Lane multiplexing at the hardware chipset level is the sole mechanism that causes both reduced PCIe lane allocation and SATA port deactivation.

Key Concept

Motherboard Chipset HSIO / Flexible I/O Lane Multiplexing and M.2 PCIe Bandwidth Sharing
Estimated Time:2m 0s
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Topics

Storage Devices and Interfaces

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