The table below details semiconductor fabrication performance metrics across eight production lines during Q2 2026:
| Fab Line | Process Node (nm) | Monthly Wafers (thousands) | Defect Density (defects/cm²) | Yield Rate (%) | R&D Intensity ($/wafer) |
|---|---|---|---|---|---|
| Line A | 3 | 45 | 0.28 | 78.5% | 420 |
| Line B | 5 | 80 | 0.22 | 84.0% | 310 |
| Line C | 7 | 120 | 0.15 | 91.2% | 180 |
| Line D | 14 | 150 | 0.08 | 95.6% | 95 |
| Line E | 3 | 35 | 0.34 | 72.0% | 460 |
| Line F | 5 | 90 | 0.18 | 86.5% | 290 |
| Line G | 7 | 110 | 0.12 | 93.0% | 210 |
| Line H | 28 | 200 | 0.04 | 98.2% | 50 |
Evaluate the truth value of the following claim regarding three boolean statements about the dataset:
Statement I: Among the Fab Lines with a Process Node of 7 nm or smaller, the median Defect Density is greater than the mean Defect Density of lines producing more than 100 thousand Monthly Wafers.
Statement II: The weighted average Yield Rate across all 3 nm and 5 nm Fab Lines combined (weighted by Monthly Wafers) is less than 82.0%.
Statement III: When the table is sorted in descending order of R&D Intensity ($/wafer), the Fab Line in the third row has a higher Yield Rate than the Fab Line with the lowest overall Defect Density.
Claim: Evaluating statements I, II, and III yields True, False, and False, respectively.
Answer: Answer